2 research outputs found
Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator
We present Ramulator 2.0, a highly modular and extensible DRAM simulator that
enables rapid and agile implementation and evaluation of design changes in the
memory controller and DRAM to meet the increasing research effort in improving
the performance, security, and reliability of memory systems. Ramulator 2.0
abstracts and models key components in a DRAM-based memory system and their
interactions into shared interfaces and independent implementations. Doing so
enables easy modification and extension of the modeled functions of the memory
controller and DRAM in Ramulator 2.0. The DRAM specification syntax of
Ramulator 2.0 is concise and human-readable, facilitating easy modifications
and extensions. Ramulator 2.0 implements a library of reusable templated lambda
functions to model the functionalities of DRAM commands to simplify the
implementation of new DRAM standards, including DDR5, LPDDR5, HBM3, and GDDR6.
We showcase Ramulator 2.0's modularity and extensibility by implementing and
evaluating a wide variety of RowHammer mitigation techniques that require
different memory controller design changes. These techniques are added
modularly as separate implementations without changing any code in the baseline
memory controller implementation. Ramulator 2.0 is rigorously validated and
maintains a fast simulation speed compared to existing cycle-accurate DRAM
simulators. Ramulator 2.0 is open-sourced under the permissive MIT license at
https://github.com/CMU-SAFARI/ramulator
TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs
Prior works propose SRAM-based TRNGs that extract entropy from SRAM arrays.
SRAM arrays are widely used in a majority of specialized or general-purpose
chips that perform the computation to store data inside the chip. Thus,
SRAM-based TRNGs present a low-cost alternative to dedicated hardware TRNGs.
However, existing SRAM-based TRNGs suffer from 1) low TRNG throughput, 2) high
energy consumption, 3) high TRNG latency, and 4) the inability to generate true
random numbers continuously, which limits the application space of SRAM-based
TRNGs. Our goal in this paper is to design an SRAM-based TRNG that overcomes
these four key limitations and thus, extends the application space of
SRAM-based TRNGs. To this end, we propose TuRaN, a new high-throughput,
energy-efficient, and low-latency SRAM-based TRNG that can sustain continuous
operation. TuRaN leverages the key observation that accessing SRAM cells
results in random access failures when the supply voltage is reduced below the
manufacturer-recommended supply voltage. TuRaN generates random numbers at high
throughput by repeatedly accessing SRAM cells with reduced supply voltage and
post-processing the resulting random faults using the SHA-256 hash function. To
demonstrate the feasibility of TuRaN, we conduct SPICE simulations on different
process nodes and analyze the potential of access failure for use as an entropy
source. We verify and support our simulation results by conducting real-world
experiments on two commercial off-the-shelf FPGA boards. We evaluate the
quality of the random numbers generated by TuRaN using the widely-adopted NIST
standard randomness tests and observe that TuRaN passes all tests. TuRaN
generates true random numbers with (i) an average (maximum) throughput of
1.6Gbps (1.812Gbps), (ii) 0.11nJ/bit energy consumption, and (iii) 278.46us
latency